A traditional TEC uses alternating n-type and p-type thermoelectric legs connected electrically in series and thermally in parallel between two ceramic substrates. When current flows, heat is absorbed at one junction (cold side) and released at the other (hot side) via the Peltier effect.

The concept places a TEC unit directly beneath a chip's hotspot region. The chip area is compartmentalized — the central high-heat-flux zone (e.g., cache) is cooled by the TEC while the surrounding lower-flux zone (e.g., logic) is handled by the MCHS ring. This targeted cooling reduces peak temperature without over-cooling the entire die.

The analytical core of the project is a compact thermal model that represents the entire radial TEC as a network of thermal resistances. Each component — chip layer, insulator, TE legs, interconnectors, central cylinder — is modelled as a resistance element. Energy balance at each node yields a linear system:

where $\mathbf{T}$ is the vector of unknown node temperatures, $\mathbf{A}$ is a block matrix of thermal conductances, and $\mathbf{B}$ contains heat generation terms (chip power, split Joule heating) and boundary conditions.

The matrix $\mathbf{A}$ has a structured block form: $\mathbf{A}_\text{chip}$ (tridiagonal — radial conduction in the chip layer), $\mathbf{A}_\text{TEC}$ (asymmetric tridiagonal — TEC layer with Peltier coupling), and $\mathbf{A}_\text{ve}$ (diagonal — vertical coupling between layers). This yields sub-millisecond solves in MATLAB, enabling rapid parameter sweeps that would be infeasible with full FEA.

The cooling capacity of each TEC stage is governed by the Peltier equation:

where $S_p, S_n$ are the Seebeck coefficients, $I$ is the operating current, $T_c, T_h$ the cold- and hot-junction temperatures, $K$ the thermal conductance, and $R$ the electrical resistance.

Thermal resistances for wedge-shaped TE legs are computed by integration over the variable cross-section:

where $A(r)$ increases linearly with radius due to the wedge geometry, and $\kappa$ is the thermal conductivity of the TE material.

The CTM's sub-millisecond solve time enables exhaustive parameter exploration that would be impossible with FEA. The MATLAB implementation evaluates the full thermal field across chip and TEC layers for any combination of design parameters.

Each objective function call simply assembles and solves the $\mathbf{A} \cdot \mathbf{T} = \mathbf{B}$ system, extracts the maximum chip temperature, and returns it to the optimizer.

The first optimization stage performs a brute-force grid search over the two integer parameters: $N$ (1–10 stages) and $M$ (4–36 wedges). For each $(N, M)$ pair, the CTM is solved and the maximum chip temperature is recorded. The matrix plot reveals the feasible design space and identifies the optimal region around $N = 7, M = 16$.

MATLAB's parallel computing toolbox was used to distribute the grid evaluation across CPU cores, evaluating all ~200 combinations in seconds.

With discrete parameters fixed, a multi-objective optimization minimizes two conflicting objectives: maximum chip temperature and total device thickness. MATLAB's gamultiobj (NSGA-II) generates a Pareto front showing the trade-off between thermal performance and fabrication complexity.

The knee-point solution was selected: $T_\text{max} = 77.8\,°\text{C}$, thickness = 264 µm, with $N = 7$ stages, $M = 16$ wedges, and 112 total TE legs.

The selected knee-point design achieves a maximum chip temperature of 77.8 °C — well below the typical junction temperature limit of 85 °C — with a total device thickness of only 264 µm.

The complete optimal parameter set includes: 7 TEC stages, 16 radial wedges, operating current of 0.3 A, TE leg length ratio $f_L = 0.65$, insulator thickness of 15 µm, and an inner radius of 1.5 mm for the central cylinder.

A parametric sweep of operating current identifies the optimal value at 0.3 A. Below this, Peltier cooling is insufficient; above it, Joule heating dominates and the device heats the chip rather than cooling it. The outward heat flux at the optimum is 0.49 W per wedge.

The COMSOL temperature contour at the optimum current shows the radial temperature gradient from the hot central region to the cooler outer periphery. The simulation confirms the design intent — heat is actively pumped outward through the TEC stages, creating a smooth temperature drop across the device.

The full coupled simulation combines the TEC unit with the circular micro-channel heat sink. The MCHS features 200 µm wide channels with 50 µm walls at an inlet velocity of 0.8 m/s. Conjugate heat transfer between the solid walls and water flow provides the final heat rejection path.

Temperature distribution in the region near the micro channels shows effective heat removal by the liquid coolant. The water temperature rises from 25 °C at the inlet to approximately 28 °C at the outlet, confirming adequate thermal capacity for the rejected heat load.